This invention relates to a highspeed semiconductor memory device capable of performing serial data access in a nibble or byte mode.
Conventionally, in a high speed dynamic type semiconductor memory device (which is hereinafter referred to as a DRAM), n pairs of data bus lines for data input and data output are provided in order to transfer n-bit serial data. That is, n-bit data is first stored in a buffer circuit provided near a data output circuit, and data is sequentially read out from the buffer circuit, in response to an output signal from in n-bit shift register, and then supplied outwardly via a data output circuit. Further, in another type of prior art DRAM, only a single pair of data bus lines are provided for each of data input and data output in this case, n bit data read out from a cell array having a plurality of divided sections are previously stored in n buffer circuits which are arranged along the data bus lines at a position far away from a data output circuit. The buffer circuits are sequentially coupled to the data bus lines in response to an output signal from an n-bit shift register, thus permitting output data from the buffer circuits to be supplied via the data output circuit.
In the data write-in mode of types of DRAM, data is transferred via the data circuit in a direction opposite to that in the data readout mode, and is stored in the n buffer circuits in the same manner as in the data readout mode.
FIGS. 1 and 2 are block diagrams of the prior art DRAMs performing data access in the case of n=8, i.e. in the byte mode.
FIG. 1 shows an example of a DRAM in which a total of 16 pairs of data bus lines including 8 pairs of data bus lines 151 for data input and 8 pairs of data bus lines 152 for data output are provided and cell array 153 is divided into eight blocks. At the time o access, it is possible to independently access one bit for each block. Thus, eight bits can be accessed as a whole. Input/output buffers 154 are connected to cell array 153, and output data selection multiplexer 155 serves to sequentially select data on 8 pairs of output data bus lines 151 at the time of data readout. Data selected by output data selection multiplexer 155 is supplied to output driver 156 which in turn supplies the data outwardly via data output pad 157. Data supplied to data input pad 158 is fed to input data selection multiplexer 160 via input driver 159. Input data selection multiplexer 160 serves to selectively and sequentially transfer data from input driver 159 to 8 pairs of input data bus lines 152, in the data write-in mode. 8 -bit shift register 161 generates, in response to a basic clock signal .phi., clock signals which are used to control the selection operations of output data selection multiplexer 155 and input data selection multiplexer 160.
FIG. 2 shows an example of a DRAM in which two pairs of data buses 171 and 172 are provided each for data input and data output and cell array 173 is divided into eight blocks, as in the case of FIG. 1. Input/ output buffers 174 are respectively connected to the eight blocks of cell array 173. Output driver 175 supplies data outwardly via data output pad 176. Data supplied to data input pad 17 is fed to input driver 178. Input/output buffer selection multiplexer 179 selectively and sequentially transfers data from eight input/output buffers 174 to output data bus 171, in the data readout mode, and sequentially transfers data on input data bus 172 to eight input/output buffers 174, in the data write-in mode. 8-bit shift register 180 generates, in response to the basic clock signal .phi., clock signals which are used to control the selection operation of input/output buffer selection multiplexer 174.
In the DRAM shown in FIG. 1, output data is selected at a stage located immediately before output driver 156, in the data readout mode, and input data is selected at a stage located immediately after input driver 159, in the data write-in mode. In this way, high speed read-out operation and write-in operation can be attained. However, a large number of data bus lines are required; in this example, as many as 16 pairs of data bus lines are needed. Even if data bus lines are commonly used for data input and data output, this still necessitates the provision of eight pairs of data bus lines. For this reason, it is necessary to provide a large wiring area around the memory cell array for circuit integration, thereby increasing the chip area.
In contrast, in the DRAM shown in FIG. 2, input/output data is selected at a stage near I/O buffers 174, and therefore, only two pairs of data bus lines are required in this example. Further, if data bus lines are commonly used for data input and data output, it is then only necessary to use one pair of data bus lines. As a result, an increase in chip area for circuit integration can be avoided, in the case of this DRAM. However, since data selection is effected at a stage far away from the input/output driver, data which is transferred via the long data bus lines will be delayed, making it difficult to attain high speed data readout and data write-in operations. Thus, in the prior art memory device capable of effecting serial access, it is not possible to reduce the chip area for circuit integration and at the same time enhance the operation speed for data readout and write-in.